1. Field of the Invention
This invention relates to a method of improving performance of a multichip cube structure, and more particularly, to a method of using foamed insulators to reduce the capacitive load of circuitry in the cube structure.
2. Description of the Related Art
To provide improved performance, manufacturers of integrated circuit devices continually strive to increase circuit density. Such devices are typically formed on a semiconductor substrate, such as a silicon wafer, and comprise a large number of miniaturized circuit elements. These elements, which include transistors, diodes, capacitors, and resistors, are usually disposed within or adjacent the substrate and define a plurality of circuit nodes. To combine the circuit elements into a useful electronic circuit, integrated circuit devices require a plurality of conducting paths that link the circuit nodes in a preferred manner. Typically, the conducting paths are provided by electrical interconnects comprising wires of aluminum or aluminum alloy that are embedded in a layer of insulating SiO2.
However, as circuit density is increased, problems associated with conventional electrical interconnects are becoming more apparent. In particular, a higher density device having an increased number of circuit elements will likely require an even greater increase in the number of electrical interconnects. Consequently, the electrical interconnects will need to have a reduced thickness and adjacent interconnects will need to be spaced more closely together. Unfortunately, such dimensional reductions tend to increase the resistance of individual interconnects and increase the capacitance between adjacent interconnects, thereby possibly increasing signal propagation delays and signal cross-talk.
This problem is particularly apparent in high density electronic packaging modules such as multichip cube structures or three-dimensional multi-chip structures. A multichip cube structure typically comprises a plurality of semiconductor chips that are adhered together in a stack. It is generally understood that each chip in the stack has conductive leads that extend to one edge of the chip so as to provide electrical contact with external circuitry. In most multichip cube structures, the conductive leads on the chips are closely spaced where adjacent leads are sometimes separated by less than 1 micron. Shrinking the distance between adjacent leads can adversely increase the capacitive load. Furthermore, stacking the chips in close proximity to one another as required in multichip cube structures can also increase the capacitive coupling between electrical interconnects on adjacent chips.
To address the problem of increased capacitive coupling between adjacent interconnects, designers have tried substituting materials having lower dielectric constants for the more commonly used oxide insulators such as SiO2. In some cases, polymers such as polyimides have been used in place of SiO2, however polyimides provide only limited improvement as the dielectric constant of polyimide (2.8–3.5) is only slightly lower than that of conventional oxide insulators. Furthermore, interconnects comprising an air bridge have also been developed as described in U.S. Pat. No. 5,891,797. The air bridge is a length of conducting material that extends from a first supported end to a second supported end through an air space such that the bridge is substantially surrounded by air. Consequently, because air has a dielectric constant that is substantially less than that of SiO2, the capacitance between adjacent interconnects is reduced. However, the use of air-bridged structures will pose some additional problems in packaging as it does not protect the metal interconnect structure from environmental attacks. They will also prove difficult to assemble in very dense packaging schemes such as multichip cube structures.
Hence from the foregoing, it will be appreciated that there is a need for a method to reduce the capacitive load of electrical interconnects in multichip cube structures. To this end, there is a particular need for a low dielectric insulating material that can isolate adjacent chips in a multichip cube structure and decrease the capacitive load of the interconnects in adjacent chips. Furthermore, there is also a need for the insulating material to retain the desirable physical and mechanical properties afforded by the conventional insulating materials used in multichip cube structure.